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| applications description features transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 document number: TXC-02050-mb ed. 3, april 1994 mrt device 6-, 8-, 34-mbit/s line interface TXC-02050 +5v equalization and rate los/loc ais control control 6-,8-,34-mbit/s line interface mrt operating rate reference frequency 6,8,34 mbit/s transmit bipolar data 6,8,34 mbit/s receive error rate clock reference bipolar data 10 -6 error rate indication clock & data nrz or p, n rail clock & data line side terminal side the transwitch multi-rate receive/transmit (mrt) device is a cmos vlsi device that provides the func- tions needed for terminating two ccitt line rates, 8448 and 34368 kbit/s, and a 6312 kbit/s rate which is speci- ?ed in the japanese ntt technical reference for high speed digital leased circuits. for 8448 and 34368 kbit/s operation, the mrt provides an optional hdb3 codec. the mrt is equipped with a receive equalizer circuit and agc. the mrt also provides a rail or nrz interface, hdb3 error rate monitor, alarm detection, and ais gener- ators. testing capability is provided by transmit and receive loopbacks. ? 6312/8448/34368 kbit/s line interface ? agc and equalizer ? line quality monitor (10 -6 error rate) ? receive loss of signal and transmit loss of clock alarms ? optional hdb3 encoder/decoder ? two loopbacks: -receive to transmit (digital) -transmit to receive (analog) ? optional transmit and receive ais generators ? rail or nrz terminal side i/o ? meets ccitt recommendation g.703 ? digital cross-connect equipment ? remote terminals ? terminal interface for multiplexers/demultiplexers ? switching systems ? csu/dsu data sheet patents pending copyright 1994 transwitch corporation txc and transwitch are registered trademarks of transwitch corporation
- 2 - mrt TXC-02050-mb ed. 3, april 1994 block diagram figure 1. mrt block diagram block diagram description on the line side, a symmetrical bipolar signal is applied to the input signal pin (di1), which requires an exter- nal 75 w termination. di2 is a dc reference voltage output which serves as an ac ground. equalization for various lengths of cable having a ? f characteristic is compensated by the two eqb0 and eqb1 signal leads. the equalization network block is connected to an agc block which has approximately a 20 db dynamic range. the agc has separate voltage and ground leads for noise immunity, and uses an exter- nal capacitor as part of an agc ?lter. the agc output is connected to the clock recovery block. the clock recovery block contains a phase-locked loop and supporting logic to generate a clock signal from the line signal. the signal lead low selects the appropriate circuit in the clock recovery block for the operat- ing frequency and provides input attenuation for the receive line signal. the line signal is monitored for loss of signal, with an alarm indication provided on the rxlos signal lead. the clock recovery block requires an external reference clock at the operating frequency (dck). the reference clock is also used for generating and sending a receive alarm indication signal (ais). the generation and sending of ais for recovered data is con- trolled by the rxais signal lead. the output of the clock recovery block is connected to the hdb3 decoder block or the output circuits block. when the decoder is enabled, indications of coding violation errors, other than the normal hdb3 zero substitu- tion codes, are provided as pulses on the signal lead labeled cv. an external clock (berck) is used to gener- ate a 10-second sampling window for detecting a 10 -6 or greater error rate. the line quality indication is provided on the signal lead labeled lqlty. line terminal side side eqb0 eqb1 low gnda agfil rxlos rxais rxdis rp/rd rn clko clko tp/td tn clki txloc dck di1 di2 tpo tno equalization network agc clock recovery hdb3 decoder i/o hdb3 encoder output driver error + - clk vagc vcoc pllc detector cv + - clk vdd gnd lbkrx cv lqlty berck pnenb dck + - clk lbktx circuits txais - 3 - mrt TXC-02050-mb ed. 3, april 1994 two terminal side interfaces are provided, a positive and negative rail (rp and rn) or nrz (rd) interface. the selection is determined by the state placed on the signal lead labeled pnenb. when a low is applied to the signal lead, the hdb3 decoder and hdb3 encoder blocks are bypassed, and the terminal side i/o is a positive and negative rail interface. when a high is applied to the signal lead, an nrz interface is provided. data is clocked out of the mrt on negative edges of the clock signal (clko). receive data and the clock sig- nals are disabled, and forced to a high impedance state by placing a low on the receive disable lead ( rxdis). for a receive positive and negative rail interface, an inverted clock ( clko) is also provided. the terminal side interface for the transmitter can either be positive and negative rail (tp and tn) or nrz (td) data depending on the state of the common control lead pnenb. data is clocked into the mrt on positive transitions of the clock signal (clki). the input clock is monitored for the loss of clock. when the input clock remains high or low, txloc will be set low. the mrt also provides the capability to generate and insert ais (all ones signal), independent of the transmit data. a low placed on the txais lead enables the transmit ais generator. two loopbacks are provided, transmit loopback and receive loopback. transmit loopback connects the data path from the transmitter output driver stage to the clock recovery, and disables the external receiver input. transmit loopback is activated by placing a low on the lbktx signal lead. receive loopback connects the receive data path to the transmit output circuits and disables the transmit input. receive loopback is activated by placing a low on the lbkrx signal lead. for 6 mbps operation, the mrt should be operated in the p and n rail mode, bypassing the hdb3 decoder/ encoder. pin diagram figure 2. mrt pin diagram with names and numbers mrt pin diagram (top view) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 pllc gnd clko clko rp/rd rn gnd vdd dck pnenb vcoc di1 di2 gnda gnd tno tpo vdd gnd vdd clki gnd tp/td tn vdd txais gnd gnd txloc rxais berck lqlty gnd eqb0 eqb1 low lbktx lbkrx vagc agfil rxdis rxlos cv vdd - 4 - mrt TXC-02050-mb ed. 3, april 1994 pin descriptions power supply and ground *note: i = input; o = output; p = power line side i/o terminal side i/o symbol pin no. i/o/p* type name/function vdd 10,18,35, 37,42 p vdd: 5-volt supply, 5%. gnd 1,6,11,16,32, 36,39,44 p ground: 0 volts reference. vagc 23 p agc vdd: isolate from vdd using 1n914 or 1n4148 diode. gnda 31 p agc groun d: 0 volts reference. symbol pin no. i/o/p type name/function di1 29 i analog data in 1: hdb3 or b8zs encoded bipolar receive data input. di2 30 o analog data in 2: dc voltage reference for data input di1. the mrt uses an internally generated voltage refer- ence as an ac ground for the received data input. an external 0.1 m f capacitor, in parallel with a 10 m f/6.3 v tantalum capacitor, is connected between this pin and ground. no other connection should be made to this pin. tno 33 o ttl24ma transmit negative out: line transmit negative; out- put is an active low. tpo 34 o ttl24ma transmit positive out: line transmit positive; output is an active low. symbol pin no. i/o/p type name/function rn 12 o ttl4ma receive negative: when pnenb is low, the hdb3 codec is bypassed and n-rail (rn) data is provided on this pin. when pnenb is high, the output is forced to a high impedance state. rp/rd 13 o ttl4ma receive positive/receive data: when pnenb is low, the hdb3 codec is bypassed and p-rail (rp) data is provided on this pin. when pnenb is high, nrz data (rd) is provided. clko 14 o cmos8ma clock out inverted: receive inverted clock output. positive and negative rail receive data is clocked out on the rising edge. disabled in the nrz mode. - 5 - mrt TXC-02050-mb ed. 3, april 1994 alarm signal outputs clko 15 o cmos8ma clock out: receive clock output. receive positive and negative rail and nrz data is clocked out on the falling edge. clki 38 i ttlr clock in: transmit clock input for p and n rail and nrz data. transmit data is clocked into the mrt on the rising edge. this clock must have a frequency of 20 ppm for the 34368 kbit/s operation and 30 ppm for the 6312/8448 kbit/s operation (ref: ccitt recom- mendation g.703). the duty cycle requirement for this clock signal is 50% 5%, measured at the 1.4v ttl threshold level. tp/td 40 i ttl transmit positive/transmit data: when pnenb is low, the hdb3 codec is bypassed and transmit p-rail (tp) data is applied to this pin. when pnenb is high, nrz transmit data (td) is applied. tn 41 i ttl transmit negative: when pnenb is low, the hdb3 codec is bypassed and transmit n-rail (tn) is applied to this pin. when pnenb is high, this input is disabled. symbol pin no. i/o/p type name/function txloc 2 o ttl2ma transmit loss of clock: active low output. a trans- mit loss of clock alarm occurs when the transmit clock input (ckli) is stuck high or low for 20-32 clock cycles. recovery occurs on the ?rst input clock transition. lqlty 5 o ttl2ma line quality: this signal represents a gross estimate of the line quality which is determined by counting coding violations for 34 (8) mbit/s operation. if the line error rate exceeds a 10 -6 threshold during a 10 (40) second interval, lqlty goes active high. lqlty is active low when coding violations do not exceed the 10 -6 threshold in a 10 (40) second interval. the output on this pin is only valid when the appropriate clock sig- nal is applied to berck. it should be disregarded in the p and n mode of operation. cv 19 o ttl2ma coding violation: active high output. a coding viola- tion pulse occurs when an hdb3 coding violation is detected in the received line data input. a coding vio- lation is not part of the hdb3 zero-substitution code. a coding violation occurs because of noise or other impairments affecting the line signal. the output of this pin should be disregarded in the p and n mode. rxlos 20 o ttl2ma receive loss of signal: active low output. a receive loss of signal occurs when the input data is zero for 20-32 clock cycles. recovery occurs when the receive signal returns. symbol pin no. i/o/p type name/function - 6 - mrt TXC-02050-mb ed. 3, april 1994 mrt control leads symbol pin no. i/o/p type name/function rxais 3 i cmosr receive alarm indication signal: when rxais is low, the mrt generates ais (all ones signal) for the terminal side receive output data. the line side receive data path is disabled. the reference clock (dck) provides the clock source required for generat- ing ais. berck 4 i ttlr bit error rate clock: this clock establishes the time base for estimating the coding violation error rate. for 34 mbit/s operation the clock frequency must be 6 khz, and for 8 mbit/s operation the clock frequency must be 1.5 khz. this pin should be left open for p and n mode operation. pnenb 8 i cmosr p and n enable: when pnenb is low, the p and n rail interface is enabled, and the hdb3 codec is bypassed. when pnenb is high, the terminal side i/o data is nrz and the hdb3 codec is enabled. this pin must be held low for 6 mbit/s operation. dck 9 i ttl reference clock: operating frequency reference clock. for receive signal clock recovery, 200 ppm frequency accuracy is adequate. if the transmit and receive ais features are used, the frequency accuracy must be 20 ppm for 34368 kbit/s and 30 ppm for 8448 and 6312 kbit/s operation. the duty cycle requirement for this clock signal is 50% 5% as mea- sured at the 1.4v ttl threshold level. rxdis 21 i cmosr receive disable: when rxdis is low, the receive side of the mrt is disabled and the rn, rp/rd, clko and clko output leads are forced to a high impedance state. lbkrx 24 i cmosr loopback receive: when lbkrx is low, the mrt loops back receive data as transmit data. the receive data is also sent to the terminal side, but the transmit data input on the terminal side is disabled. (note 1) lbktx 25 i cmosr loopback transmit: when lbktx is low, the mrt loops back transmit data as receive data. the transmit data is sent on the line side, but the receive data input on the line side is disabled. (note 1) low 26 i cmosr low frequency: when low is low, the mrt enables equalization and input attenuator settings for 6312 or 8448 kbit/s operation. this lead also controls the clock recovery high/low frequency range circuit. note 1: setting lbktx and lbkrx low simultaneously will cause invalid outputs at the receive terminal and transmit line ports. - 7 - mrt TXC-02050-mb ed. 3, april 1994 pins with external components eqb1 eqb0 27 28 i i cmosr equalizer bit 1: msb of equalizer setting. equalizer bit 0: lsb of equalizer setting. equalization is as follows for 34 mbit/s operation: eqb1 eqb0 cable equaliza tion ? f * 1 1 0db< cable <3.5db 1 0 2.6db - 9 - mrt TXC-02050-mb ed. 3, april 1994 input, output, and i/o parameters input parameters for ttl input parameters for ttlr note: input has a 100k (nominal) internal pull-up resistor. input parameters for cmosr note: input has a 100k (nominal) internal pull-up resistor. output parameters for ttl2ma parameter min typ max unit test conditions v ih 2.0 v 4.75 - 11 - mrt TXC-02050-mb ed. 3, april 1994 timing characteristics detailed timing diagrams for the mrt are illustrated in figures 3 through 9. all output times are measured with maximum load capacitance appropriate for the pin type. timing parameters are measured at (v oh - v ol )/2 or (v ih - v il )/2 as applicable. line side timing characteristics the line side timing characteristics of the mrt are designed so that the line output mask at the transformer output meets the wave shapes speci?ed in ccitt recommendation g.703 for 34 and 8 mbit/s operation and the ntt technical reference for high speed digital leased circuit service for 6 mbit/s operation. the pulse masks for each of the three modes of operation are shown in figures 3, 4, and 5. refer to the corresponding standard cited in each case for further details regarding the interface. figure 3. pulse mask at the 34368 kbit/s interface 17 ns (14.55 + 2.45) v 1.0 0.5 0 8.65 ns (14.55 - 5.90) 14.55 ns 12.1 ns (14.55 - 2.45) 24.5 ns (14.55 + 9.95) 29.1 ns (14.55 + 14.55) nominal pulse 0.1 0.1 0.1 0.1 0.1 0.1 reference: ccitt recommendation g.703 0.2 0.2 - 12 - mrt TXC-02050-mb ed. 3, april 1994 figure 4. pulse mask at the 8448 kbit/s interface figure 5. pulse mask at the 6312 kbit/s interface 69 ns (59 + 10) v 2.370 1.185 0 35 ns (59 - 24) 59 ns 49 ns (59 - 10) 100 ns (59 + 41) 118 ns (59 + 59) nominal pulse 0.237 0.237 0.237 0.237 0.237 0.237 0.474 reference: ccitt recommendation g.703 0.474 pulse amplitude a nominal pulse shape (0,2) (0,1) b c d e (0,0) (4,0) time f g h i horizontal axis 20 ns/div vertical axis 1 v/div reference: ntt technical reference for high-speed digital leased circuit services coordinates of each point a : ( 0, 2.3) f : ( 0, 1.7) b : (2.4, 2.3) g : (0.4, 1.7) c : (2.4, 1.0) h : (1.6, 0.9) d : (3.2, 0.3) i : (1.6, 0.3) e : (4.0, 0.3) - 13 - mrt TXC-02050-mb ed. 3, april 1994 terminal side timing characteristics figure 6. nrz transmit input note 1: clki symmetry is measured about the 1.4vdc threshold in order to assure symmetric output waveforms. note 2: the clock input can be 6, 8, or 34 mhz (refer to page 5). figure 7. nrz receive output note 1: cklo symmetry is measured about the 50% amplitude point. note 2: the clock output can be 6, 8, or 34 mhz (refer to page 4). parameter symbol min typ max unit clki clock period t cyc note 2 ns clki duty cycle (t pwh /t cyc )--45 55% tp,td set-up time to clki - t su 3ns tp,td hold time after clki - t h 2ns parameter symbol min typ max unit clko clock period t cyc note 2 ns clko duty cycle (t pwh /t cyc )--45 55% rp,rd output delay after clko t od(1) -5 5 ns cv output delay after clko t od(2) -5 5 ns data valid data valid data valid clki 1.4v tp,td t su t pwh t h t cyc clko rp,rd cv t pwh t cyc t od(1) t od(2) - 14 - mrt TXC-02050-mb ed. 3, april 1994 figure 8. p and n rail transmit input note 1: clki symmetry is measured about the 1.4vdc threshold. note 2: the clock input can be 6, 8, or 34 mhz (refer to page 5). figure 9. p and n rail receive timing note 1: clko symmetry is measured about the 50% amplitude point. note 2: the clock output can be 6, 8, or 34 mhz (refer to page 4). parameter symbol min typ max unit clki clock period t cyc note 2 ns clki duty cycle (t pwh /t cyc )--45 55% tp,td & tn set-up time to clki - t su 3ns tp,td & tn hold time after clki - t h 2ns parameter symbol min typ max unit clko clock period t cyc note 2 ns clko duty cycle (t pwh /t cyc )--4555% clko output delay after clko - t od(1) 2ns rp, rd and rn output delay after clko t od(2) -5 6 ns data valid data valid data valid clki 1.4v tp,td t su t pwh t cyc t h data valid data valid data valid tn clko rp,rd t pwh t cyc t od(1) t od(2) rn clko - 15 - mrt TXC-02050-mb ed. 3, april 1994 operation power supply figure 10. mrt power supply connections the mrt device has separate power supply pins labeled vdd and vagc. the vagc supply pin is connected to the internal agc ampli?er and requires isolation from the vdd supply as indicated in figure 10. separate bypass networks must be used for connecting the vdd and vagc supply pins on the mrt to +5v. the bypass network on the vagc pin consists of an in4148 or in914 diode, and a 10/6.3 volt microfarad (tantalum) capac- itor connected in parallel with a 0.1 microfarad capacitor, as shown in figure 10. transwitch recommends that the 0.1 microfarad decoupling capacitors be of rf quality and that they be connected in close proximity to the device. TXC-02050 gnd gnd gnd gnd gnd gnd gnd gnd gnda vdd vdd vdd vdd vdd vagc 10/6.3v 10/6.3v all capacitors are 0.1 microfarad unless otherwise 1 6 11 16 32 36 39 44 23 31 10 18 35 37 42 +5v speci?ed + + in914 or in4148 a a a d d d d d d d d ferrite bead fair rite 2743002111 a - 16 - mrt TXC-02050-mb ed. 3, april 1994 overview line side input impedance the input impedance of the mrt is a function of the state of the low lead and the operating rate. table 1 lists the input impedance of the mrt at the operating line rates (which are 1/2 the bit rates). line side input sensitivity the input voltage sensitivity of the mrt depends on the state of the low lead as shown in table 2 below. line side input circuit the circuit shown in figure 11 illustrates the component required for operating the mrt device for 34368, 8448 or 6312 kbit/s. the transformer should have a frequency response of 0.2 to 80 mhz with an insertion loss of 1 db, maximum. transwitch recommends the use of a coilcraft transformer (part no. wb-1010) or equiva- lent). this gives return loss and isolation voltage values that meet or exceed requirements. figure 11. line side input circuit line side output characteristics the line side output of the mrt switches from rail to rail on both of its output leads, tpo and tno. this pro- vides the maximum voltage swing, and makes the output voltage depend on the +5 volt power supply input to the chip. the external circuit design must therefore be done with care in order to assure the meeting of the amplitude requirements. table 1. mrt input impedance condition minimum input impedance, | z | low = 1, line rate = 17184 kbit/s 1260 ohms low = 0, line rate = 4224 kbit/s 2390 ohms low = 0, line rate = 3156 kbit/s 3670 ohms table 2. mrt input sensitivity low lead input sensitivity (peak volts) min max 0 0.5 2.7 (6 & 8 mbit/s) 1 0.15 1.1 (34 mbit/s) TXC-02050 mrt device 1 : 1 receive data input 10/6.3 10/6.3 0.1 0.1 75 5% + + 29 30 - 17 - mrt TXC-02050-mb ed. 3, april 1994 line side output circuits figure 12 illustrates the output circuit required for operating the mrt device for a 34368 kbit/s application. the transformer and resistors shown assure that the output waveform meets the ccitt mask for 34368 kbit/s transmission and that the mrt device is operated within the current limits of the ttl24ma output parameters on page 10. the transformer should have a frequency response of 0.1 - 100 mhz with an insertion loss of 1db, maximum. figure 12. line side output circuit outline (34368 kbit/s) figure 13 shows a variation of the circuit in figure 12. this circuit improves performance in applications when a plastic device is mounted in a socket. the additional low-pass ?lter compensates for possible overshoot caused by inductance created by the device/socket interface. the transformer should have a frequency response of 0.1 - 100 mhz with an insertion loss of 1db, maximum. figure 13. line side output circuit outline (34368 kbit/s) the peak voltage and current output requirements for 6312 and 8448 kbit/s operation are different from that required for 34368 kbit/s operation. the output circuit in figure 14 illustrates the output circuit required for 6312 kbit/s and 8448 kbit/s operation. the transformer should have a frequency response of .01 - 50 mhz with an insertion loss of 1db, maximum. the transformer, drivers and resistors assure that the output waveform meets the ccitt masks for these rates and that the mrt device is operated within the current limits of the ttl24ma output parameters on page 10. figure 14. line side output circuit outline (8448 and 6312 kbit/s) TXC-02050 mrt device 1 : 2 150 150 transmit data output 34 33 TXC-02050 mrt device 1 : 2 75 75 transmit data output 100 100 18 pf 18 pf 34 33 TXC-02050 mrt device 1 : 1 r1 r2 transmit data output act11034 34 33 for 8448 kbit/s operation: r1 and r2 = 27 w for 6312 kbit/s operation: r1 and r2 = 36 w - 18 - mrt TXC-02050-mb ed. 3, april 1994 jitter tolerance ccitt recommendation g.823 speci?es that network equipment must be able to accommodate and tolerate levels of jitter up to certain speci?ed limits. the mrt accommodates and tolerates more input jitter than the level of input jitter speci?ed by the ccitt. with input jitter applied to the mrt line side receive input di1 (pin 29), the mrt properly recovers clock, decodes the hdb3, and outputs error-free nrz data over (and beyond) the ccitt speci?ed jitter input and frequency ranges. performance characteristics are shown below in figure 15 (34.368 mbit/s operation) and figure 16 (8.448 mbit/s operation). figure 15. mrt jitter tolerance at34.368 mbit/s (v dd = 5v, t a = 25 o c) figure 16. mrt jitter tolerance at 8.448 mbit/s (v dd = 5v, t a = 25 o c) 10.0 0.1 10hz 100hz 1khz 100khz log scale 30 khz measured minimum requirement log scale acceptance range 1mhz 10khz 1.0 ccitt rec. g.823 limit input jitter ui (peak- peak) frequency 10.0 0.1 10hz 100hz 1khz 100khz 10 khz measured minimum requirement log scale acceptance range input jitter ui (peak- peak) 1mhz 10khz 1.0 ccitt rec. g.823 limit frequency - 19 - mrt TXC-02050-mb ed. 3, april 1994 maximum output jitter in absence of input jitter ccitt recommendation g.823 speci?es that it is necessary to restrict the amount of jitter generated by indi- vidual equipments. the actual limits depend on the type of equipment (and application). in the absence of applied jitter, the receive path of the mrt introduces a maximum 0.05 unit intervals (uis) peak-to-peak jitter over the following frequency ranges: at 8.448 mbit/s: 20 hz to 400 khz at 34.368 mbit/s: 100 hz to 800 khz this operation is with the mrt terminated by the external components (and component values) speci?ed in the pin description table for pin 7 (vcoc), pin 17 (pllc), and pin 22 (agfil). jitter transfer transfer of jitter through an individual equipment is characterized by the relationship between the applied input jitter and the resulting output jitter as a function of frequency. ccitt recommendation g.823 speci?es that it is important to restrict jitter gain. with applied input jitter at the mrt receive terminals, the maximum mrt output jitter is not greater than the level of input jitter plus 0.05 ui peak-to-peak jitter. this operation is over the same ccitt speci?ed frequency ranges and mrt external terminations as described in the above maximum output jitter section. interfering tone tolerance the mrt will properly recover clock and present error-free output to the receive terminal side interface in the presence of a prbs interfering tone with the same data sequence as the data input for the following line rates: *prbs = pseudo-random binary sequence table 3. interfering tone tolerance data rate (mbit/s) tone rate (mbit/s) maximum tone level data sequence 34.368 34.368 100ppm -18 db 2 23 -1 8.448 8.448 100ppm -4 db 2 15 - 1 6.312 6.312 100ppm -4 db 2 15 - 1 - 20 - mrt TXC-02050-mb ed. 3, april 1994 packaging the mrt device is packaged in a 44-pin plastic leaded chip carrier suitable for socket or surface mounting. all dimensions shown are in inches and are nominal unless otherwise noted. figure 17. mrt 44-pin plastic leaded chip carrier transwitch 40 6 29 39 17 7 28 18 .500 (nom) sq. .650 (nom) sq. .075 .149 .170 nom. bottom view top view 40 6 29 39 17 7 28 18 1 1 nom. .690 (nom) sq. .050 typ .015 typ - 21 - mrt TXC-02050-mb ed. 3, april 1994 ordering information part number: TXC-02050-aipl 44-pin plastic leaded chip carrier related products txc-03701 e2/e3f framer vlsi device. the e2/e3 framer directly interfaces with the mrt and provides multi-mode framing for ccitt g.751/g.753 (34368 kbit/s) or ccitt g.742/ g.745 (8448 kbit/s) signals. txc-03702 jt2f framer vlsi device. the jt2f framer directly interfaces with the mrt and provides framing for ccitt g.704 (6312 kbit/s) signals. txc-21055 mrt evaluation board. a complete ready-to-use single board that demonstrates the functions and features of the mrt line interface vlsi device. - 22 - mrt TXC-02050-mb ed. 3, april 1994 standards documentation sources telecommunication technical standards and reference documentation may be obtain from the following organizations: ansi (u.s.a.): american national standards institute (ansi) 11 west 42nd street new york, new york 10036 tel: 212-642-4900 fax: 212-302-1286 bellcore (u.s.a.): bellcore attention - customer service 8 corporate place piscataway, nj 08854 tel: 800-521-core (in u.s.a.) tel: 908-699-5800 fax: 908-336-2559 ccitt: publication services of itu place des nations ch 1211 geneve 20, switzerland tel: 41-22-730-5285 fax: 41-22-730-5991 ttc (japan): ttc standard publishing group of the telecommunications technology committee 2nd floor, hamamatsucho - suzuki building, 1 2-11, hamamatsu-cho, minato-ku, tokyo tel: 81-3-3432-1551 fax: 81-3-3432-1553 - 23 - mrt TXC-02050-mb ed. 3, april 1994 list of data sheet changes this change list identi?es those areas within the updated mrt data sheet that have technical differences rel- ative to the superseded mrt data sheet: updated mrt data sheet: edition 3, april 1994 superseded mrt data sheet: edition 2, february 1992 the page numbers indicated below of the updated data sheet include changes relative to the superseded data sheet. page number of updated data sheet summary of the change all changed edition number and date on all pages. all removed preliminary designation. 2 changed direction of di2 pin in figure 1, block diagram. 2-3 made minor edits to block diagram description. 4 replaced description of pin 30, di2. 5 edited descriptions of pins 5 (lqlty) and 38 (clki). 6 made minor edits to descriptions of pins 4 (berck), 24 ( lbkrx) and 25 ( lbktx). also added note 1 at bottom of page. 7 added value for f in description of pins 27 and 28 (eqb1 and eqb0), and replaced description of pin 7 (vcoc). 8 added values to ?rst row of thermal characteristics table and removed second row. 11-12 made minor clari?cations to second paragraph of text and to figures 3, 4, and 5. 13 deleted note 3 below figure 7. 14 deleted note 3 below figure 9. 15 made minor changes to figure 10. 16 added two sentences to line side input circuit text. 17 made minor edits to figure 13 and to the paragraph of text below it. 17 made minor changes to figure 14. 18 added jitter generation paragraph. 18 changed jitter transfer text at bottom of page. 19 changed interfering tone tolerance text, added the data sequence col- umn to table 3, and removed table 4. 20 removed ceramic packaging diagram and added measurements to figure 17, plastic packaging diagram. 22 added standards documentation sources. - 24 - mrt TXC-02050-mb ed. 3, april 1994 - notes - - 25 - mrt TXC-02050-mb ed. 3, april 1994 - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. transwitch vlsi: powering communication innovation transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 - 27 - mrt TXC-02050-mb ed. 3, april 1994 documentation update registration form if you would like be added to our database of customers who have registered to receive updated documenta- tion for this device as it becomes available, please provide your name and address below, and fax or mail this page to mary koch at transwitch. mary will ensure that relevant product information sheets, data sheets, application notes and technical bulletins are sent to you. please print or type the information requested below, or attach a business card. name: ________________________________________________________________________ title: _________________________________________________________________________ company: _____________________________________________________________________ dept./mailstop: ________________________________________________________________ street: _______________________________________________________________________ city/state/zip: _________________________________________________________________ if located outside u.s.a., please add - postal code: ___________ country: ______________ telephone:______________________________________________ ext.: _________________ fax: __________________________________ e-mail: _______________________________ purchasing dept. location: _______________________________________________________ please describe brie?y your intended application for this device, and indicate whether you would care to have a transwitch applications engineer contact you to provide assistance: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ please fax this page to mary koch at (203) 926-9453 or fold, tape and mail it (see other side) transwitch vlsi: powering communication innovation transwitch corporation ? 8 progress drive ???? shelton, ct 06484 usa tel: 203-929-8810 fax: 203-926-9453 transwitch corporation attention: mary koch 8 progress drive shelton, ct 06484 u.s.a. first class postage required please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes avail- able. (fold back on this line ?rst.) (fold back on this line second, then tape closed, stamp and mail.) |
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